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2023-10-21Introduced opcodes for NOT, OR, AND, XOR and EQAryadev Chavali
Does a bit level version of each of these.
2023-10-21Cleaned up and used macro magic to shorten the INST_* macrosAryadev Chavali
Instead of having 3 differing macros for each typed version of each opcode, just supply the type as a symbol to the macro, which will concatenated the type to all the places necessary. Relies on D(BYTE|HWORD|WORD) and OP_*_(BYTE|HWORD|WORD) being a consistent naming style.
2023-10-21Helper functions for read/write instructions from darr or FILE*Aryadev Chavali
2023-10-21Switched from floats to halfwordAryadev Chavali
Registers are now just words, with pushing from and moving to registers with specified subtypes just pushing those types into the word registers. That means there are 8 word registers which can act as 16 half word registers, which themselves can act as 64 byte registers.
2023-10-16Added opcode_as_cstr, opcode_type_as_cstr and inst_printAryadev Chavali
Pretty self explanatory, helps with logging.
2023-10-16Fixed error with OP_PUSH where bits weren't in the pattern of data_type_tAryadev Chavali
2023-10-16MOV and PUSH_*_REGISTER should only need bytes for their operandAryadev Chavali
We won't have more than 255 registers, so a byte is all that's necessary.
2023-10-16Added functionality to read and write instruction bytecodeAryadev Chavali
Uses some bit hacks to quickly check what data type an opcode may have by shifting down to units then casting it to a data_type_t. Not very well tested yet, we'll need to see now.
2023-10-16Made OP_HALT the only instruction to have the top byte filledAryadev Chavali
2023-10-16MOV now uses the stack, removed register member in inst_tAryadev Chavali
Instead of taking an operand and a register, mov just uses the stack for the operand. Therefore, there's no need for a register member in inst_t. As a result, PUSH_*_REGISTER now uses the operand for the register.
2023-10-15Better checking of opcode typesAryadev Chavali
Introduced an enum (opcode_type_t) for the masks and values of each opcode, which allows defining a single enum which checks an opcode by a opcode_type_t.
2023-10-15Remove parameter for INST_*POPAryadev Chavali
POP instructions do not require an operand: they're a unary operator.
2023-10-15Set register parameter for inst_t to be a byteAryadev Chavali
We at most have 255 registers, so no need to have a word for it.
2023-10-15Renamed opcodes PUSH_*REG to PUSH_*_REGISTERAryadev Chavali
More precise in naming
2023-10-15Rearranged opcodes (switched mov with push_reg)Aryadev Chavali
This is so push opcodes are closer together
2023-10-15Added instructions to push register values onto the stackAryadev Chavali
2023-10-15Added instructions for popping differing typesAryadev Chavali
Bit mask is 100.
2023-10-15Added opcodes for MOV and ability for instructions to hold registersAryadev Chavali
Pretty simple implementation
2023-10-15Make push opcodes a specific bit set and add a NOOP opcodeAryadev Chavali
By default, a zero initialised set of instructions are NOOPs, which is great. Last two bits of a push opcode is always 01. Rest of the bits are used to distinguish between differing types of push. This makes it easier to inspect on the byte level what type of opcode we have.
2023-10-15Split off instruction structure to its own fileAryadev Chavali
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